SH-2A Datasheet, PDF (42/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 3 Exception Handling
3.7.2 Trap Instruction
When a TRAPA instruction is executed, trap instruction exception handling is started. The CPU
operates as follows.
1. The start address of the exception service routine corresponding to the vector number specified
by the TRAPA instruction is fetched from the exception handling vector table.
2. The status register (SR) is saved on the stack.
3. The program counter (PC) is saved on the stack. The saved PC value is the start address of the
instruction following the TRAPA instruction.
4. Execution jumps to the address fetched from the exception handling vector table and program
execution commences. The jump is not a delayed branch.
3.7.3 Slot Illegal Instructions
An instruction located immediately after a delayed branch instruction is said to be located in the
delay slot. If the instruction in the delay slot is undefined code, slot illegal instruction exception
handling is started when that undefined code is decoded. Also, if the instruction in the delay slot
is one that modifies the program counter (PC), slot illegal instruction exception handling is started
when that instruction is decoded. Moreover, in the case of a product that does not have an FPU, or
if the FPU is in the module standby state, a floating-point instruction or FPU-related instruction is
treated as undefined code, and if located in a delay slot, will cause slot illegal instruction exception
handling to be started when decoded. In addition, if the product that does not have a register bank,
register bank-related instructions are treated as undefined code. If located in a delay slot, when
decoded they will cause slot illegal instruction handling to be started.
Furthermore, if an instruction located in a delay slot is a 32-bit instruction, RESBANK instruction,
DIVS instruction, or DIVU instruction, slot illegal instruction exception handling will be started
when this instruction is decoded.
CPU operations in slot illegal instruction exception handling are as follows.
1. The start address of the exception service routine is fetched from the exception handling vector
table.
2. The status register (SR) is saved on the stack.
3. The program counter (PC) is saved on the stack. The saved PC value is the jump destination
address of the delayed branch instruction immediately preceding an undefined code,
instruction that overwrites the PC, 32-bit instruction, RESBANK instruction, DIVS
instruction, or DIVU instruction.
4. Execution jumps to the address fetched from the exception handling vector table and program
execution commences. The jump is not a delayed branch.
Rev. 3.00 Jul 08, 2005 page 28 of 484
REJ09B0051-0300