SH-2A Datasheet, PDF (41/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

3.7 Instruction Exceptions
Section 3 Exception Handling
3.7.1 Types of Instruction Exception
There are five kinds of instruction that can initiate exception handling: the TRAP instruction, slot
illegal instructions, general illegal instructions, integer division instructions, and floating-point
operation instructions. These are summarized in table 3.8.
Table 3.8 Instruction Exception Types
Type
Trap instruction
Slot illegal
instruction
General illegal
instruction
Integer division
exception
Floating-point
operation
instruction
Source Instruction
TRAPA
Undefined code (FPU instruction or
FPU-related CPU instruction in module
standby status including FPU or in
product with no FPU, or register bank-
related instruction in product with no
register bank) located immediately after
delayed branch instruction (in delay
slot), instruction that modifies PC, 32-
bit instruction, RESBANK instruction,
DIVS instruction, or DIVU instruction
Undefined code (FPU instruction, FPU-
related CPU instruction, or register
bank-related instruction in module
standby status including FPU or in
product with no FPU) not in delay slot
Division by zero
Negative maximum value ÷ (-1)
Instruction causing invalid operation
defined by IEEE754 standard or
division-by-zero exception, instruction
causing overflow, underflow, or inexact
exception
Notes
Delayed branch instructions: JMP,
JSR, BRA, BSR, RTS, RTE, BF/S,
BT/S, BSRF, BRAF
Register bank-related instructions:
RESBANK, LDBANK, STBANK
Instructions that modify PC: JMP,
JSR, BRA, BSR, RTS, RTE, BT, BF,
TRAPA, BF/S, BT/S, BSRF, BRAF,
JSR/N, RTV/N
32-bit instructions: BAND.B,
BANDNOT.B, BCLR.B, BLD.B,
BLDNOT.B, BOR.B, BORNOT.B,
BSET.B, BST.B, BXOR.B, FMOV.S
@disp12, FMOV.D @disp12,
MOV.B @disp12, MOV.W @disp12,
MOV.L @disp12, MOVI20,
MOVI20S, MOVU.B, MOVU.W
DIVU, DIVS
DIVS
FADD, FSUB, FMUL, FDIV, FMAC,
FCMP/EQ, FCMP/GT, FLOAT,
FTRC, FCNVDS, FCNVSD, FSQRT
Rev. 3.00 Jul 08, 2005 page 27 of 484
REJ09B0051-0300