SH-2A Datasheet, PDF (373/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
Floating-point arithmetic
operation instruction
(single-precision)
(FADD FR1,FR2)
(latency 3 → latency 1)
Next floating-point
instruction (single-
precision)
(FMOV FR2,FR2)
⋅ ⋅ ⋅ DF E1 E2 SF
— DF EX NA SF
Figure 8.49 Example of Contention Due to Overwriting (Except FDIV, FSQRT)
If a write is performed by the following instruction on the register used as a source register by a
double-precision FADD, FSUB, or FMUL, the following will be kept waiting for 2 cycles (figure
8.50).
Floating-point arithmetic
operation instruction
(double-precision)
(FADD DR0,DR2)
(latency 0 → latency 2)
Next floating-point
load/store instruction
(single-precision)
(FMOV FR4,FR1)
IF DF E1 E1 E1 E1 E1 E1 E2 SF
IF — — DF EX NA SF
Figure 8.50 Example of Write to Double-Precision Instruction Source Immediately after
Double-Precision Operation
Rev. 3.00 Jul 08, 2005 page 359 of 484
REJ09B0051-0300