SH-2A Datasheet, PDF (364/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
8.3.7 Details of Contention Due to Branch Instruction
The following rules apply to contention due to a branch instruction.
(1) Parallel execution is possible when the branch instruction does not branch.
(2) When a branch instruction is supplied as a succeeding instruction, parallel execution with the
preceding instruction is possible regardless of the branching situation.
(3) When a branch instruction is supplied as a preceding instruction, parallel execution with the
succeeding instruction is not possible if a branch occurs. Parallel execution is not possible
even if IF has already been completed for the delay slot (figure 8.32).
(4) For the delay slot, ID is performed in the next slot in which there is a branch instruction EX
stage.
(5) Execution of a delayed branch instruction is delayed if a fetch has not been performed for the
delay slot.
A relevant example is shown in figure 8.28.
ADD R3,R4
IF ID EX
JMP @R2
IF ID EX
Delay slot
IF — ID EX
Branch destination instruction
IF ID
Figure 8.32 Example of Contention between Branch Instructions
Rev. 3.00 Jul 08, 2005 page 350 of 484
REJ09B0051-0300