SH-2A Datasheet, PDF (458/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
When there is banking and no overflow, saving to the bank is performed automatically. The
pipeline ends after eight stages: IF, ID, EX, EX, MA, MA, MA, EX.
When there is banking and overflow, registers saved to the bank are automatically restored, and
the BO bit is set to 1. The pipeline ends after 27 stages: IF, ID, EX, EX, MA, MA, MA, EX, MA,
MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA.
After the first two stages there are two repetitions of EX, three repetitions of MA, one EX, and 19
repetitions of MA.
Interrupt exception handling is not a delayed branch. The IF stage of the branch destination
instruction is started from the slot containing the third MA stage of the interrupt exception
handling.
Interrupt sources comprise external interrupt request pins such as NMI, a user break, and interrupts
by on-chip peripheral modules.
Interrupt Acceptance
Interrupt exception handling is not accepted in a delay slot.
If a multi-cycle instruction is currently being executed, interrupt exception handling is not
accepted until after execution of that instruction is completed. However, a DIVU or DIVS
instruction can be canceled during execution, allowing the interrupt to be accepted.
Rev. 3.00 Jul 08, 2005 page 444 of 484
REJ09B0051-0300