SH-2A Datasheet, PDF (172/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.4.2
ADDC
Binary Addition
with Carry
ADD with Carry
Format
ADDC Rm,Rn
Abstract
Rn + Rm + T → Rn, carry → T
Arithmetic Instruction
Code
Cycle T Bit
0011nnnnmmmm1110 1
Carry
Description
Adds Rm data and the T bit to general register Rn data, and stores the result in Rn. The T bit
changes according to the result. This instruction can add data that has more than 32 bits.
Operation
ADDC (long m,long n)
/* ADDC Rm,Rn */
{
unsigned long tmp0,tmp1;
tmp1=R[n]+R[m];
tmp0=R[n];
R[n]=tmp1+T;
if (tmp0>tmp1) T=1;
else T=0;
if (tmp1>R[n]) T=1;
PC+=2;
}
Examples:
CLRT
ADDC R3,R1
ADDC R2,R0
; R0:R1 (64 bits) + R2:R3 (64 bits) = R0:R1 (64 bits)
; Before execution: T = 0, R1 = H'00000001, R3 = H'FFFFFFFF
; After execution: T = 1, R1 = H'0000000
; Before execution: T = 1, R0 = H'00000000, R2 = H'00000000
; After execution: T = 0, R0 = H'00000001
Rev. 3.00 Jul 08, 2005 page 158 of 484
REJ09B0051-0300