SH-2A Datasheet, PDF (107/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
Operation
BCLRM (long d, long i, long n)
{
long disp, imm, temp;
/*BCLR.B #imm3, @(disp12, Rn) */
disp = (0x00000FFF & (long)d);
imm= (0x00000007&(long)i);
temp= (long) Read_Byte (R[n]+disp);
temp&=(~(0x00000001<<imm));
Write_Byte (R[n]+disp, temp);
PC+=4;
}
BCLR (long i, long n)
{
long imm, temp;
/*BCLR #imm3, Rn */
imm= (0x00000007 &(long)i);
R[n]&=(~(0x00000001<<imm));
PC+=2;
}
Examples:
BCLR.B #H'5,@(2,R0) ; Before execution: @(R0 + 2) = H'FF
; After execution: @(R0 + 2) = H'DF
BCLR #H'4, R0
; Before execution: @R0 = H'FFFFFFFF
; After execution: @R0 = H'FFFFFFFF
Rev. 3.00 Jul 08, 2005 page 93 of 484
REJ09B0051-0300