SH-2A Datasheet, PDF (385/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
Type
Category
Number Execution
of Stages States
Branch
Conditional
3
instructions branch
instructions
3/1^*1
Delayed
3
conditional
branch
instructions
2/1^*1
Latency Contention
3/1^*1
2/1^*1
• These instruc-
tions use the
branch pipeline.
• These instruc-
tions use the
branch pipeline.
BF
BT
BS/F
BT/S
Instructions
label
label
label
label
Unconditio
3
nal branch
instructions
2
2 • These instruc- BRA
label
tions use the
branch pipeline.
BRAF
Rm
BSR
label
BSRF Rm
JMP
@Rm
JSR
@Rm
RTS
Unconditio
3
nal branch
instructions
with no
delay
5
3
3 • These instruc- JSR/N @Rm
tions use the
branch pipeline.
RTS/N
RTV/N Rm
5
5 • This instruction JSR/N @@(disp,TBR)
uses the branch
pipeline.
• This instruction
uses the
memory access
pipeline.
System System
3
control
control
instructions ALU
5
instructions
3
1
1
3
2
1
1
—
CLRT
LDC
Rm,SR
—
LDC
Rm,GBR
LDC
Rm,TBR
LDC
Rm,VBR
LDS
Rm,PR
0
NOP
SETT
4
2
2
STC
SR,Rn
3
1
1
STC
GBR,Rn
STC
TBR,Rn
STC
VBR,Rn
STS
PR,Rn
Rev. 3.00 Jul 08, 2005 page 371 of 484
REJ09B0051-0300