SH-2A Datasheet, PDF (63/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 5 Instruction Set
Instruction
Classification Type
Op Code
Logic operation 6
instructions
AND
NOT
OR
TAS
TST
XOR
Shift instructions 12
ROTL
ROTR
ROTCL
ROTCR
SHAD
SHAL
SHAR
SHLD
SHLL
SHLLn
SHLR
SHLRn
Function
Logical AND
Bit inversion
Logical OR
Memory test and bit setting
Logical AND T bit setting
Exclusive logical OR
1-bit left rotation
1-bit right rotation
1-bit left rotation with T bit
1-bit right rotation with T bit
Dynamic arithmetic shift
Arithmetic 1-bit left shift
Arithmetic 1-bit right shift
Dynamic logical shift
Logical 1-bit left shift
Logical n-bit left shift
Logical 1-bit right shift
Logical n-bit right shift
Number of
Instructions
14
16
Rev. 3.00 Jul 08, 2005 page 49 of 484
REJ09B0051-0300