SH-2A Datasheet, PDF (335/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.5.20 LDS
Load to FPU
System Register
LoaD to FPU System
register
Section 6 Instruction Descriptions
System Control Instruction
Format
Abstract
Code
Cycle
LDS Rm,FPUL
Rm → FPUL
0100mmmm01011010 1
LDS.L @Rm+,FPUL (Rm) → FPUL, Rm+4 → Rm 0100mmmm01010110 1
LDS Rm,FPSCR
Rm → FPSCR
0100mmmm01101010 1
LDS.L @Rm+,FPSCR (Rm) → FPSCR, Rm+4 → Rm 0100mmmm01100110 1
T Bit
—
—
—
—
Description
This instruction loads the source operand into FPU system registers FPUL and FPSCR.
Operation
#define FPSCR_MASK 0x003FFFFF
LDSFPUL(int m, int *FPUL)
/* LDS Rm,FPUL */
{
*FPUL=R[m];
PC+=2;
}
LDSMFPUL(int m, int *FPUL)
/* LDS.L @Rm+,FPUL */
{
*FPUL=Read_Long(R[m]);
R[m]+=4;
PC+=2;
}
LDSFPSCR(int m)
/* LDS Rm,FPSCR */
{
FPSCR=R[m] & FPSCR_MASK;
PC+=2;
}
LDSMFPSCR(int m)
/* LDS.L @Rm+,FPSCR */
{
Rev. 3.00 Jul 08, 2005 page 321 of 484
REJ09B0051-0300