SH-2A Datasheet, PDF (8/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

3.6.1 Interrupt Sources.................................................................................................. 25
3.6.2 Interrupt Priority .................................................................................................. 25
3.6.3 Interrupt Exception Handling .............................................................................. 26
3.7 Instruction Exceptions ...................................................................................................... 27
3.7.1 Types of Instruction Exception............................................................................ 27
3.7.2 Trap Instruction ................................................................................................... 28
3.7.3 Slot Illegal Instructions........................................................................................ 28
3.7.4 General Illegal Instructions.................................................................................. 29
3.7.5 Integer Division Instructions ............................................................................... 29
3.7.6 Floating-Point Operation Instructions.................................................................. 29
3.8 Cases in Which Exceptions Are Not Accepted................................................................. 30
3.9 Stack Status after Exception Handling.............................................................................. 31
3.10 Usage Notes ...................................................................................................................... 32
3.10.1 Stack Pointer (SP) Value ..................................................................................... 32
3.10.2 Vector Base Register (VBR) Value ..................................................................... 32
3.10.3 Address Errors Occurring in Address Error Exception Handling Stacking......... 32
Section 4 Instruction Features ......................................................................................... 33
4.1 RISC-Type Instruction Set................................................................................................ 33
4.2 Addressing Modes ............................................................................................................ 37
4.3 Instruction Format............................................................................................................. 41
Section 5 Instruction Set.................................................................................................... 47
5.1 Instruction Set by Classification ....................................................................................... 47
5.1.1 Data Transfer Instructions ................................................................................... 54
5.1.2 Arithmetic Operation Instructions ....................................................................... 58
5.1.3 Logic Operation Instructions ............................................................................... 61
5.1.4 Shift Instructions.................................................................................................. 62
5.1.5 Branch Instructions.............................................................................................. 63
5.1.6 System Control Instructions................................................................................. 64
5.1.7 Floating-Point Instructions .................................................................................. 66
5.1.8 FPU-Related CPU Instructions............................................................................ 68
5.1.9 Bit Manipulation Instructions .............................................................................. 69
Section 6 Instruction Descriptions.................................................................................. 71
6.1 Overview of New Instructions .......................................................................................... 71
6.2 Format of Instruction Descriptions ................................................................................... 75
6.3 New Instructions ............................................................................................................... 88
6.3.1 BAND......... Bit AND ...................................... Bit Manipulation Instruction ... 88
6.3.2 BANDNOT Bit ANDNOT .............................. Bit Manipulation Instruction ... 90
6.3.3 BCLR ......... Bit CLeaR .................................... Bit Manipulation Instruction ... 92
Rev. 3.00 Jul 08, 2005 page viii of xiv