SH-2A Datasheet, PDF (471/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

(10) Floating-Point Register Load Instructions
Section 8 Pipeline Operation
Instruction Types
FMOV.S
FMOV.S
FMOV.S
FMOV.D
FMOV.D
FMOV.D
@Rm,FRn
@Rm+,FRn
@(R0,Rm),FRn
@Rm,DRn
@Rm,DRn
@(R0,Rm),DRn
Pipeline
• Single-Precision
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA
: CPU pipeline
IF DF EX NA SF
: FPU pipeline
IF ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF DF E1 E2 SF
: FPU pipeline
IF ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF DF E1 E2 SF
: FPU pipeline
• Double-Precision
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA MA
: CPU pipeline
IF DF EX EX NA SF
: FPU pipeline
IF — ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF — DF E1 E2 SF
: FPU pipeline
IF — ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF — DF E1 E2 SF
: FPU pipeline
Rev. 3.00 Jul 08, 2005 page 457 of 484
REJ09B0051-0300