SH-2A Datasheet, PDF (473/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(11) Floating-Point Register Load Instruction (12-Bit Displacement)
Instruction Type
FMOV.S @(disp12,Rm),FRn
FMOV.D @(disp12,Rm),DRn
Pipeline
• Single-Precision
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA
: CPU pipeline
IF DF EX NA SF
: FPU pipeline
IF ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF DF EX NA SF
: FPU pipeline
IF ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF DF E1 E2 SF
: FPU pipeline
• Double-Precision
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA MA
: CPU pipeline
IF DF EX EX NA SF
: FPU pipeline
IF — ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF — DF E1 E2 SF
: FPU pipeline
IF — ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF — DF E1 E2 SF : FPU pipeline
Operation
• Single-Precision
The CPU pipeline ends after four stages – IF, ID, EX, MA – and the FPU pipeline after five
stages – IF, DF, EX, NA, SF. Contention may occur if an instruction that reads the destination
of this instruction is located within the 3 instructions following this instruction.
• Double-Precision
The CPU pipeline ends after five stages – IF, ID, EX, MA, MA – and the FPU pipeline after
six stages – IF, DF, EX, EX, NA, SF. Contention may occur if an instruction that reads the
destination of this instruction is located within the 3 instructions following this instruction.
Rev. 3.00 Jul 08, 2005 page 459 of 484
REJ09B0051-0300