SH-2A Datasheet, PDF (55/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 4 Instruction Features
Addressing Instruction
Mode
Format
Immediate #imm:8
addressing
#imm:8
#imm:8
#imm:3
Effective Addresses Calculation
The 8-bit immediate data (imm) for the TST, AND,
OR, and XOR instructions are zero-extended.
The 8-bit immediate data (imm) for the MOV, ADD,
and CMP/EQ instructions are sign-extended.
Immediate data (imm) for the TRAPA instruction is
zero-extended and is quadrupled.
3-bit immediate data imm of BAND, BOR, BXOR,
BST, BLD, BSET, or BCLR instruction indicates bit
position.
Formula
—
—
—
—
4.3 Instruction Format
The instruction format table, table 5.8, refers to the source operand and the destination operand.
The meaning of the operand depends on the instruction code. The symbols are used as follows:
xxxx: Instruction code
mmmm: Source register
nnnn: Destination register
iiii: Immediate data
dddd: Displacement
Rev. 3.00 Jul 08, 2005 page 41 of 484
REJ09B0051-0300