SH-2A Datasheet, PDF (464/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(3) FPUL Store Instruction (STS)
Instruction Type
STS FPUL,Rn
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX WB
: CPU pipeline
IF DF EX NA
: FPU pipeline
IF ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF DF ⋅ ⋅ ⋅
: FPU pipeline
IF ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF DF ⋅ ⋅ ⋅
: FPU pipeline
Operation
The CPU pipeline ends after four stages – IF, ID, EX, WB – and the FPU pipeline after four stages
– IF, DF, EX, NA. Contention may occur if an instruction that uses the destination of this
instruction is located within the 3 instructions following this instruction.
Instruction Issuance
This instruction uses the multiplication result read path.
This instruction uses the FPU load/store pipeline and memory access pipeline.
There is no contention with a CPU memory write instruction.
If FPUL is waiting for the result of an FPU arithmetic operation, the latency of the previous
instruction is reduced by 2. See section 8.6, Contention Due to FPU, for details.
Parallel Execution Capability
No particular comments
Rev. 3.00 Jul 08, 2005 page 450 of 484
REJ09B0051-0300