SH-2A Datasheet, PDF (85/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
Section 6 Instruction Descriptions
6.1 Overview of New Instructions
In the SH-2A/SH2A-FPU, new instructions have been added in vacant locations other than
instruction codes assigned to SH-2E CPU instructions (instruction codes with upper 4 bits of 0000
to 1110) and SH4 FPU instructions (instruction codes with upper 4 bits of 1111). However, the
SH-2A does not support the following SH4 FPU instructions: (a) FMOV instructions specifying
XDm/XDn, (b) the FRCHG instruction, and (c) FIPR, and FTRV instructions.
This section gives detailed descriptions of the new instructions.
CPU instructions
(SH2E + new instructions)
FPU instructions
(SH4, excluding (a), (b), and (c))
SH-2A
0000 ^{. . .}
to
1110 ^{. . .}
1111 ^{. . .}
The new instructions are those described in (1) to (14) below. (1) to (3) are 32-bit fixed-length
instructions, and (4) to (14) are 16-bit fixed-length instructions.
(1) Immediate Transfer Instructions
MOVI20, MOVI20S
These instructions transfer 20-bit immediate data in the instruction code to a register.
Combination with one of these instructions simplifies generation of a 28-bit address, making it
possible to specify on-chip memory addresses for a maximum of 256 MB.
Rev. 3.00 Jul 08, 2005 page 71 of 484
REJ09B0051-0300