SH-2A Datasheet, PDF (219/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.4.27
LDS
Load to System
Register
LoaD to System register
Section 6 Instruction Descriptions
System Control Instruction
Format
LDS Rm,MACH
LDS Rm,MACL
LDS Rm,PR
LDS.L @Rm+, MACH
LDS.L @Rm+, MACL
LDS.L @Rm+,PR
Abstract
Rm → MACH
Rm → MACL
Rm → PR
(Rm) → MACH, Rm + 4 → Rm
(Rm) → MACL, Rm + 4 → Rm
(Rm) → PR, Rm + 4 → Rm
Code
0100mmmm00001010
0100mmmm00011010
0100mmmm00101010
0100mmmm00000110
0100mmmm00010110
0100mmmm00100110
Cycle
1
1
1
1
1
1
T Bit
—
—
—
—
—
—
Description
Store the source operand into the system register MACH, MACL, or PR.
Operation
LDSMACH(long m)
/* LDS Rm,MACH */
{
MACH=R[m];
PC+=2;
}
LDSMACL(long m)
/* LDS Rm,MACL */
{
MACL=R[m];
PC+=2;
}
LDSPR(long m)
/* LDS Rm,PR */
{
PR=R[m];
PC+=2;
}
LDSMMACH(long m)
/* LDS.L @Rm+,MACH */
{
MACH=Read_Long(R[m]);
Rev. 3.00 Jul 08, 2005 page 205 of 484
REJ09B0051-0300