SH-2A Datasheet, PDF (15/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 1 Overview
Section 1 Overview
1.1 Features
The SH-2A/SH2A-FPU is a 32-bit RISC (reduced instruction set computer) microprocessor that is
upward-compatible with the SH-1, SH-2, and SH-2E at the object code level. The SH2A-FPU has
an on-chip floating point unit and the SH-2A does not. The use of 16-bit basic instructions enables
code efficiency, performance, and ease of use to be improved.
Features of the SH-2A/SH2A-FPU are summarized in table 1.1.
Table 1.1
Item
CPU
SH-2A/SH2A-FPU Features
Features
• Original Renesas Technology architecture
• 32-bit internal data bus
• General-register architecture
 Sixteen 32-bit general registers
 Four 32-bit control registers
 Four 32-bit system registers
 Register banks for fast interrupt response
• RISC-type instruction set (upward-compatible with SH Series)
 Instruction length: 16-bit basic instructions for improved efficiency,
and 32-bit instructions for improved performance and ease of use
 Load-store architecture
 Delayed branch instructions
 Instruction set based on C language
• Superscalar architecture allowing simultaneous execution of two
instructions, including FPU
• Instruction execution time: Max. 2 instructions/cycle
• Address space: 4 Gbytes
• On-chip multiplier
• Five-stage pipeline
• Harvard architecture
Rev. 3.00 Jul 08, 2005 page 1 of 484
REJ09B0051-0300