SH-2A Datasheet, PDF (212/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.4.23 EXTU
Zero Extension
EXTend as Unsigned
Arithmetic Instruction
Format
EXTU.B Rm, Rn
EXTU.W Rm, Rn
Abstract
Zero-extend Rm from byte → Rn
Zero-extend Rm from word → Rn
Code
Cycle T Bit
0110nnnnmmmm1100 1
—
0110nnnnmmmm1101 1
—
Description
Zero-extends general register Rm data, and stores the result in Rn. If byte length is specified, 0s
are written in bits 8 to 31 of Rn. If word length is specified, 0s are written in bits 16 to 31 of Rn.
Operation
EXTUB(long m,long n)
{
R[n]=R[m];
R[n]&=0x000000FF;
PC+=2;
}
EXTUW(long m,long n)
{
R[n]=R[m];
R[n]&=0x0000FFFF;
PC+=2;
}
/* EXTU.B Rm,Rn */
/* EXTU.W Rm,Rn */
Examples:
EXTU.B R0,R1
EXTU.W R0,R1
; Before execution:
; After execution:
; Before execution:
; After execution:
R0 = H'FFFFFF80
R1 = H'00000080
R0 = H'FFFF8000
R1 = H'00008000
Rev. 3.00 Jul 08, 2005 page 198 of 484
REJ09B0051-0300