SH-2A Datasheet, PDF (258/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.4.48 RTE
ReTurn from Exception
Return from Exception Handling
System Control Instruction
Delayed Branch Instruction
Format
RTE
Abstract
Delayed branch, Stack area → PC/SR
Code
Cycle T Bit
0000000000101011 4
LSB
Description
Returns from an interrupt routine. The PC and SR values are restored from the stack, and the
program continues from the address specified by the restored PC value. The T bit is used as the
LSB bit in the SR register restored from the stack area.
Note
Since this is a delayed branch instruction, the instruction after this RTE is executed before
branching. No address errors and interrupts are accepted between this instruction and the next
instruction. If the next instruction is a branch instruction, it is acknowledged as an illegal slot
instruction.
Operation
RTE() /* RTE */
{
unsigned long temp;
temp=PC;
PC=Read_Long(R[15])+4;
R[15]+=4;
SR=Read_Long(R[15])&0x000063F3;
R[15]+=4;
Delay_Slot(temp+2);
}
Rev. 3.00 Jul 08, 2005 page 244 of 484
REJ09B0051-0300