SH-2A Datasheet, PDF (322/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.5.13
FMUL
Floating-Point
Multiplication
Floating-point MULtiply
Floating-Point Instruction
PR Format
Abstract
0 FMUL FRm,FRn FRn*FRm → FRn
1 FMUL DRm,DRn DRn*DRm → DRn
Code
Cycle
1111nnnnmmmm0010 1
1111nnn0mmm00010 6
T Bit
—
—
Description
When FPSCR.PR = 0: Arithmetically multiplies the two single-precision floating-point numbers
in FRn and FRm, and stores the result in FRn.
When FPSCR.PR = 1: Arithmetically multiplies the two double-precision floating-point numbers
in DRn and DRm, and stores the result in DRn.
When FPSCR.enable.O/U/I is set, an FPU exception trap is generated regardless of whether or not
an exception has occurred. When an exception occurs, correct exception information is reflected in
FPSCR.cause and FPSCR.flag, and FRn or DRn is not updated. Appropriate processing should
therefore be performed by software.
Operation
void FMUL(int m,n)
{
pc += 2;
clear_cause();
if((data_type_of(m) == sNaN) ||
(data_type_of(n) == sNaN)) invalid(n);
else if((data_type_of(m) == qNaN) ||
(data_type_of(n) == qNaN)) qnan(n);
else switch (data_type_of(m){
case NORM: switch (data_type_of(n)){
case PZERO:
case NZERO: zero(n,sign_of(m)^sign_of(n)); break;
case PINF:
case NINF:
inf(n,sign_of(m)^sign_of(n)); break;
default:
normal_fmul(m,n); break;
Rev. 3.00 Jul 08, 2005 page 308 of 484
REJ09B0051-0300