SH-2A Datasheet, PDF (431/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(b) When condition is not met
If it is determined in the ID stage that the condition is not met, processing proceeds with
nothing done in the EX stage. The next instruction is fetched and executed.
A typical pipeline is shown below.
If the preceding instruction is a CMP instruction, execution is delayed by 1 cycle.
CMP
BF/S
Delay slot
↔ ↔ ↔ ↔ ↔ Slots
IF ID EX
IF — ID EX
IF — — ID
If the preceding instruction is a single-precision FCMP instruction, execution is delayed by 2
cycles.
FCMP/single
BF/S
Delay slot
↔ ↔ ↔ ↔ ↔ ↔ Slots
IF DF E1 E2
IF — — ID EX
IF — — — ID
If the preceding instruction is a double-precision FCMP instruction, execution is delayed by 3
cycles.
FCMP/double
BF/S
Delay slot
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF DF E1 E1 E2
IF — — — ID EX
IF — — — — ID
Instruction Issuance
These instructions use the branch pipeline.
If an instruction fetch has not yet been performed for the instruction (delay slot) immediately
following one of these instructions, execution of that instruction is delayed.
Parallel Execution Capability
No particular comments
Rev. 3.00 Jul 08, 2005 page 417 of 484
REJ09B0051-0300