SH-2A Datasheet, PDF (493/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Appendix A SH-2A/SH2A-FPU Parallel Execution
Appendix A SH-2A/SH2A-FPU Parallel Execution
The table below can be used to determine whether or not parallel execution is supported,
depending on the type of arithmetic unit used. In the case of instructions that belong to more than
one category, parallel execution is supported if all of the applicable intersections are marked with
a circle (o).
First
(1) BR
instruction _{(2) MR}
(3) MW
(4) MF
(5) ML
(6) MU
(7) SF
(8) FL
(9) FP
(10) FC
(11) EX
Second instruction
(1) BR
×
o
o
o
o
o
o
o
(2) MR (3) MW
o
o
×
×
×
×
o
×
o
o
o
o
o
o
o
o
(4) MF
o
o
×
×
o
o
o
o
(5) ML
o
o
o
o
×
o
o
o
(6) MU
o
o
o
o
o
×
o
o
(7) SF
o
o
o
o
o
o
×
o
o
o
o
o
o
o
o
×
×
×
×
×
×
×
o
o
o
o
o
o
o
(8) FL
o
o
o
o
o
o
o
×
o
×
o
(9) FP (10) FC (11) EX
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
×
o
×
×
o
×
×
×
o
o
o
Classifi- Classifi-
cation of cation of
First
Second
Instruction Instruction
BR
BR
BF
BT/S
BRA
JSR
RTS/N
MR
MR
LDC.L
MOV.B
MOV.B
MOV.B
MOV.W
MOV.W
MOV.L
MOV.L
MOV.L
MOVU.W
PREF
disp
disp
disp
@Rm
@Rm+,GBR
@(disp,GBR),R0
@Rm,Rn
@(disp12,Rm),Rn
@(R0,Rm),Rn
@-Rm,R0
@(disp,GBR),R0
@Rm,Rn
@(disp12,Rm),Rn
@(disp12,Rm),Rn
@Rn
Instruction
BF/S
BSR
BRAF
JSR/N
RTV/N
LDC.L
MOV.B
MOV.B
MOV.W
MOV.W
MOV.W
MOV.L
MOV.L
MOV.L
MOVML.L
disp
disp
Rm
@Rm
Rm
@Rm+,VBR
@(disp,Rm),R0
@Rm+,Rn
@(disp,GBR),R0
@Rm,Rn
@(disp12,Rm),Rn
@(disp,Rm),Rn
@Rm+,Rn
@(disp,PC),Rn
@R15+,Rn
BT
BSRF
JMP
RTS
TRAPA
LDS.L
MOV.B
MOV.B
MOV.W
MOV.W
MOV.W
MOV.L
MOV.L
MOVU.B
MOVMU.L
disp
Rm
@Rm
#imm
@Rm+,PR
@(R0,Rm),Rn
@-Rm,R0
@(disp,Rm),R0
@Rm+,Rn
@(disp,PC),Rn
@(R0,Rm),Rn
@-Rm,R0
@(disp12,Rm),Rn
@R15+,Rn
Rev. 3.00 Jul 08, 2005 page 479 of 484
REJ09B0051-0300