SH-2A Datasheet, PDF (33/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 3 Exception Handling
The vector numbers and vector table address offsets are shown in table 3.3, and the method of
calculating the vector table address in table 3.4.
Table 3.3 Exception Vector Table
Exception Source
Vector Number Vector Table Address Offset
Power-on reset
PC
0
H'00000000 to H'00000003
SP
1
H'00000004 to H'00000007
Manual reset
PC
2
H'00000008 to H'0000000B
SP
3
H'0000000C to H'0000000F
General illegal instruction
4
H'00000010 to H'00000013
RAM error
5
H'00000014 to H'00000017
Slot illegal instruction
6
H'00000018 to H'0000001B
(Reserved for system)
7
H'0000001C to H'0000001F
8
H'00000020 to H'00000023
CPU address error
9
H'00000024 to H'00000027
DMAC address error
10
H'00000028 to H'0000002B
Interrupt
NMI
11
H'0000002C to H'0000002F
User break
12
H'00000030 to H'00000033
FPU exception
13
H'00000034 to H'00000037
H-UDI
14
H'00000038to H'0000003B
Bank overflow
15
H'0000003C to H'0000003F
Bank underflow
16
H'00000040 to H'00000043
Integer division exception
17
(division by zero)
H'00000044 to H'00000047
Integer division exception (overflow) 18
H'00000048 to H'0000004B
(Reserved for system)
19
•
31
H'0000004C to H'0000004F
•
H'0000007C to H'0000007F
Trap instruction (user vector)
32
•
63
H'00000080 to H'00000083
•
H'000000FC to H'000000FF
External interrupt (IRQ), on-chip
64
peripheral module^*
•
511
H'00000100 to H'00000103
•
H'000007FC to H'000007FF
Note: * For the vector numbers and address offsets of external interrupts and on-chip peripheral
module interrupts, see “Internal Module Interrupt Exception Handling Vectors and Priority
Order” in the Interrupt Controller section of the hardware manual.
Rev. 3.00 Jul 08, 2005 page 19 of 484
REJ09B0051-0300