SH-2A Datasheet, PDF (455/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(16) TRAP Instruction
Instruction Type
TRAPA #imm
Pipeline
Instruction A
Next instruction
Instruction after next
Branch destination
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX EX EX MA MA MA
IF — ⋅ ⋅ ⋅
IF — ⋅ ⋅ ⋅
IF
Operation
The pipeline ends after eight stages: IF, ID, EX, EX, EX, MA, MA, MA. A TRAP instruction is
not a delayed branch instruction. The IF stage of the branch destination instruction is started from
the slot containing the third MA of the TRAP instruction.
Instruction Issuance
This instruction uses the memory access pipeline.
Parallel Execution Capability
This is a multi-cycle instruction, and cannot be executed in parallel with a subsequent instruction.
Rev. 3.00 Jul 08, 2005 page 441 of 484
REJ09B0051-0300