SH-2A Datasheet, PDF (268/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.4.55
SHLR
One-Bit Right
Logical Shift
SHift Logical Right
Shift Instruction
Format
SHLR Rn
Abstract
0 → Rn → T
Code
0100nnnn00000001
Cycle
1
T Bit
LSB
Description
Logically shifts the contents of general register Rn to the right by one bit, and stores the result in
Rn. The bit that is shifted out of the operand is transferred to the T bit (figure 6.11).
SHLR
MSB
0
LSB
T
Figure 6.11 Shift Logical Right
Operation
SHLR(long n) /* SHLR Rn */
{
if ((R[n]&0x00000001)==0) T=0;
else T=1;
R[n]>>=1;
R[n]&=0x7FFFFFFF;
PC+=2;
}
Examples:
SHLR R0
; Before execution:
; After execution:
R0 = H'80000001, T = 0
R0 = H'40000000, T = 1
Rev. 3.00 Jul 08, 2005 page 254 of 484
REJ09B0051-0300