SH-2A Datasheet, PDF (287/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.4.67
XOR
Exclusive
Logical OR
eXclusive OR logical
Section 6 Instruction Descriptions
Logical Instruction
Format
Abstract
Code
XOR Rm,Rn
XOR #imm,R0
XOR.B #imm,
@(R0,GBR)
Rn ^ Rm → Rn
R0 ^ imm → R0
(R0 + GBR) ^ imm → (R0 + GBR)
0010nnnnmmmm1010
11001010iiiiiiii
11001110iiiiiiii
Cycle T Bit
1
—
1
—
3
—
Description
Exclusive ORs the contents of general registers Rn and Rm, and stores the result in Rn. The
contents of general register R0 can also be exclusive ORed with zero-extended 8-bit immediate
data, or 8-bit memory accessed by indirect indexed GBR addressing can be exclusive ORed with
8-bit immediate data.
Rev. 3.00 Jul 08, 2005 page 273 of 484
REJ09B0051-0300