SH-2A Datasheet, PDF (38/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 3 Exception Handling
3.5 Register Bank Errors
3.5.1 Register Bank Error Sources
(1) Bank Overflow
When a save has already been performed to all register bank areas when acceptance of register
overflow exception has been set by interrupt controller, and an interrupt that uses a register
bank is generated and is accepted by the CPU
(2) Bank Underflow
When an attempt is made to execute a RESBANK instruction when a save has not been
performed to a register bank
3.5.2 Register Bank Error Exception Handling
Register bank error exception handling is started when a register bank error occurs. CPU
operations are as follows.
1. The start address of the exception service routine corresponding to the register bank error is
fetched from the exception handling vector table.
2. The status register (SR) is saved on the stack.
3. The program counter (PC) is saved on the stack. The saved PC value is the start address of the
instruction following the last instruction executed, in the case of a bank overflow, or the start
address of the executed RESBANK instruction, in the case of an underflow. To prevent
multiple interrupts when a bank overflow occurs, the level of the interrupt that is the source of
the bank overflow is written to the interrupt mask level bits (I3 to I0) in the status register
(SR).
4. Execution jumps to the address fetched from the exception handling vector table and program
execution commences. The jump is not a delayed branch.
Rev. 3.00 Jul 08, 2005 page 24 of 484
REJ09B0051-0300