SH-2A Datasheet, PDF (434/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(4) No Delay Unconditional Branch Instructions
Instruction Types
JSR/N @Rm
RTS/N
RTV/N Rm
Pipeline
Instruction A
Next instruction
Instruction after next
Second instruction
after next
Branch destination
instruction
↔ ↔ ↔ ↔ ↔ Slots
IF ID EX
IF — ⋅ ⋅ ⋅ (Fetched but discarded)
IF ⋅ ⋅ ⋅ (Fetched but discarded)
IF ⋅ ⋅ ⋅ (Fetched but discarded)
— IF ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after three stages: IF, ID, EX. Condition determination is performed in the ID
stage. Conditional branch instructions are not delayed branch instructions. The branch destination
address is calculated in the EX stage. All overrun-fetched instructions up to that point are
discarded. The branch destination instruction fetch is started from the slot following the
instruction A EX stage slot.
Instruction Issuance
These instructions use the branch pipeline.
Parallel Execution Capability
No particular comments
Rev. 3.00 Jul 08, 2005 page 420 of 484
REJ09B0051-0300