SH-2A Datasheet, PDF (460/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(3) Illegal Instruction Exception Handling
Instruction Type
Illegal instruction exception handling
Pipeline
Illegal instruction
Next instruction
Instruction after next
Branch destination
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX EX MA MA MA
IF — ⋅ ⋅ ⋅
IF — ⋅ ⋅ ⋅
IF ID
Operation
An illegal instruction is accepted in the ID stage of an instruction, and processing from that ID
stage onward is replaced by the illegal instruction exception handling sequence. The pipeline ends
after seven stages: IF, ID, EX, EX, MA, MA, MA. Illegal instruction exception handling is not a
delayed branch.
Address error generation sources comprise those related to general illegal instructions and those
related to slot illegal instructions. When undefined code located other than in the slot immediately
after a delayed branch instruction (called the delay slot) is decoded, general illegal instruction
exception handling is performed. When undefined core located in the delay slot is decoded, or an
instruction that modifies the program counter, and a 32-bit instruction, and a RESBANK
instruction, and a DIVU or DIVS instruction are located in the delay slot and decoded, slot illegal
instruction handling is performed.
General illegal instruction exception handling is also performed if an FPU instruction or FPU-
related CPU instruction is executed while the FPU is in the module stopped state.
The IF stage of the branch destination instruction is started from the slot containing the last MA
stage of the illegal instruction exception handling.
Rev. 3.00 Jul 08, 2005 page 446 of 484
REJ09B0051-0300