SH-2A Datasheet, PDF (407/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
MAC.W @Rm+,@Rn+
STS MACL,Rn
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA MA mm mm
IF — — — — ID EX WB
IF — — — ID EX ⋅ ⋅ ⋅
(c) When a MAC.W instruction is immediately followed by an LDS.L (memory) instruction
Execution is delayed for a MAC execution state (3-slot) interval.
MAC.W @Rm+,@Rn+
LDS.L @Rn+,MACL
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA MA mm mm
IF — — — ID EX MA WB
IF — — ID EX ⋅ ⋅ ⋅
Instruction Issuance
This instruction uses the memory access pipeline.
This instruction uses the multiplier.
This instruction is executed even if the multiplier is locked.
This instruction locks the multiplier for a 4-slot interval.
Parallel Execution Capability
This is a multi-cycle instruction, and cannot be executed in parallel with a subsequent instruction.
(See section 8.3.4, Details of Contention Due to Multi-Cycle Instruction.)
Rev. 3.00 Jul 08, 2005 page 393 of 484
REJ09B0051-0300