SH-2A Datasheet, PDF (228/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.4.30 MOV
Data Transfer
MOVe data
Data Transfer Instruction
Format
MOV
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
Rm,Rn
Rm,@Rn
Rm,@Rn
Rm,@Rn
@Rm,Rn
@Rm,Rn
@Rm,Rn
Rm,@–Rn
Rm,@–Rn
Rm,@–Rn
@Rm+,Rn
MOV.W @Rm+,Rn
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
@Rm+,Rn
Rm,@(R0,Rn)
Rm,@(R0,Rn)
Rm,@(R0,Rn)
@(R0,Rm),Rn
@(R0,Rm),Rn
@(R0,Rm),Rn
Abstract
Rm → Rn
Rm → (Rn)
Rm → (Rn)
Rm → (Rn)
(Rm) → sign extension → Rn
(Rm) → sign extension → Rn
(Rm) → Rn
Rn – 1 → Rn, Rm → (Rn)
Rn – 2 → Rn, Rm → (Rn)
Rn – 4 → Rn, Rm → (Rn)
(Rm) → sign extension → Rn,
Rm + 1 → Rm
(Rm) → sign extension → Rn,
Rm + 2 → Rm
(Rm) → Rn, Rm + 4 → Rm
Rm → (R0 + Rn)
Rm → (R0 + Rn)
Rm → (R0 + Rn)
(R0 + Rm) → sign extension → Rn
(R0 + Rm) → sign extension → Rn
(R0 + Rm) → Rn
Code
0110nnnnmmmm0011
0010nnnnmmmm0000
0010nnnnmmmm0001
0010nnnnmmmm0010
0110nnnnmmmm0000
0110nnnnmmmm0001
0110nnnnmmmm0010
0010nnnnmmmm0100
0010nnnnmmmm0101
0010nnnnmmmm0110
0110nnnnmmmm0100
Cycle T Bit
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
0110nnnnmmmm0101 1
—
0110nnnnmmmm0110 1
—
0000nnnnmmmm0100 1
—
0000nnnnmmmm0101 1
—
0000nnnnmmmm0110 1
—
0000nnnnmmmm1100 1
—
0000nnnnmmmm1101 1
—
0000nnnnmmmm1110 1
—
Description
Transfers the source operand to the destination. When the operand is stored in memory, the
transferred data can be a byte, word, or longword. Loaded data from memory is stored in a register
after it is sign-extended to a longword.
Rev. 3.00 Jul 08, 2005 page 214 of 484
REJ09B0051-0300