SH-2A Datasheet, PDF (156/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.3.27 MULR
MULtiply to Register
Rn Result Storage Signed Multiplication
Arithmetic Instruction
SH-2A/SH2A-FPU (New)
Format
MULR R0,Rn
Abstract
R0 × Rn → Rn
Code
0100nnnn10000000
Cycle
2
T Bit
―
Description
Performs 32-bit multiplication of the contents of general register R0 by Rn, and stores the lower
32 bits of the result in general register Rn.
Operation
MULR (long n) /* MULR
{
R[n] = R[0]*R[n];
PC+=2;
}
R0, Rn */
Examples:
MULR R0,R1
; Before execution: R0 = H'FFFFFFFE, R1 = H'00005555
; After execution: R1 = H'FFFF5556
Rev. 3.00 Jul 08, 2005 page 142 of 484
REJ09B0051-0300