SH-2A Datasheet, PDF (429/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(a) When condition is met
The branch destination address is calculated in the EX stage. All overrun-fetched instructions
up to that point are discarded. The branch destination instruction fetch is started from the slot
following the instruction A EX stage slot.
(b) When condition is not met
If it is determined in the ID stage that the condition is not met, processing proceeds with
nothing done in the EX stage. The next instruction is fetched and executed.
A typical pipeline is shown below.
If the preceding instruction is a CMP instruction, execution is delayed by 1 cycle.
CMP
BF
Branch destination
↔ ↔ ↔ ↔ ↔ Slots
IF ID EX
IF — ID EX
IF
If the preceding instruction is a single-precision FCMP instruction, execution is delayed by 2
cycles.
FCMP/single
BF
Branch destination
↔ ↔ ↔ ↔ ↔ ↔ Slots
IF DF E1 E2
IF — — ID EX
IF
If the preceding instruction is a double-precision FCMP instruction, execution is delayed by 3
cycles.
FCMP/double
BF
Branch destination
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF DF E1 E1 E2
IF — — — ID EX
IF
Instruction Issuance
These instructions use the branch pipeline.
Parallel Execution Capability
No particular comments
Rev. 3.00 Jul 08, 2005 page 415 of 484
REJ09B0051-0300