SH-2A Datasheet, PDF (76/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 5 Instruction Set
5.1.4 Shift Instructions
Table 5.6 Shift Instructions
Instruction
ROTL
ROTR
ROTCL
ROTCR
SHAD
Rn
Rn
Rn
Rn
Rm, Rn
SHAL
SHAR
SHLD
Rn
Rn
Rm, Rn
SHLL
Rn
SHLR
Rn
SHLL2 Rn
SHLR2 Rn
SHLL8 Rn
SHLR8 Rn
SHLL16 Rn
SHLR16 Rn
Compatibility
Code
Operation
Cycles
T Bit
New
SH2E
SH4
SH-2A/
SH2A-
FPU
0100nnnn00000100 T ← Rn ← MSB
1
MSB Yes Yes
0100nnnn00000101 LSB → Rn → T
1
LSB Yes Yes
0100nnnn00100100 T ← Rn ← T
1
MSB Yes Yes
0100nnnn00100101 T → Rn → T
1
LSB Yes Yes
0100nnnnmmmm1100 When Rm ≥ 0, Rn<<Rm → Rn
1
―
Yes
When Rm < 0, Rn>>|Rm| → [MSB →
Rn]
0100nnnn00100000 T ← Rn ← 0
1
MSB Yes Yes
0100nnnn00100001 MSB → Rn → T
1
LSB Yes Yes
0100nnnnmmmm1101 When Rm ≥ 0, Rn<<Rm → Rn
1
―
Yes
When Rm < 0, Rn>>|Rm| → [0 → Rn]
0100nnnn00000000 T ← Rn ← 0
1
MSB Yes Yes
0100nnnn00000001 0 → Rn → T
1
LSB Yes Yes
0100nnnn00001000 Rn<<2 → Rn
1
― Yes Yes
0100nnnn00001001 Rn>>2 → Rn
1
― Yes Yes
0100nnnn00011000 Rn<<8 → Rn
1
― Yes Yes
0100nnnn00011001 Rn>>8 → Rn
1
― Yes Yes
0100nnnn00101000 Rn<<16 → Rn
1
― Yes Yes
0100nnnn00101001 Rn>>16 → Rn
1
― Yes Yes
Rev. 3.00 Jul 08, 2005 page 62 of 484
REJ09B0051-0300