SH-2A Datasheet, PDF (413/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(b) When a MUL.L instruction is immediately followed by a MULS.W, MULU.W, DMULS.L,
DMULU.L, MUL.L, MULR, STS (register). STS.L (memory), or LDS (register) instruction
As the MUL.L instruction locks the multiplier, stalling occurs a further 2-slot interval back.
MUL.L Rm,Rn
STS MACL,Rn
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID mm mm mm
IF — — ID EX WB
IF — ID EX ⋅ ⋅ ⋅
(c) When a MUL.L instruction is immediately followed by an LDS.L (memory) instruction
Execution is delayed during execution of MUL.L (two cycles).
MUL.L
LDS.L @Rn+,MACL
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID mm mm mm
IF — — ID EX MA WB
IF — ID EX ⋅ ⋅ ⋅
Instruction Issuance
These instructions use the multiplier.
These instructions lock the multiplier for a 2-slot interval.
Parallel Execution Capability
These are multi-cycle instructions, and cannot be executed in parallel with a subsequent
instruction. (See section 8.3.4, Details of Contention Due to Multi-Cycle Instruction.)
Rev. 3.00 Jul 08, 2005 page 399 of 484
REJ09B0051-0300