SH-2A Datasheet, PDF (332/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.5.19 FTRC
Conversion
to Integer
Floating-point TRuncate
and Convert to integer
Floating-Point Instruction
PR Format
Abstract
0
FTRC FRm,FPUL (long)FRm → FPUL
1
FTRC DRm,FPUL (long)DRm → FPUL
Code
Cycle
1111mmmm00111101 1
1111mmm000111101 2
T Bit
—
—
Description
When FPSCR.PR = 0: Converts the single-precision floating-point number in FRm to a 32-bit
integer, and stores the result in FPUL.
When FPSCR.PR = 1: Converts the double-precision floating-point number in FRm to a 32-bit
integer, and stores the result in FPUL.
The rounding mode is always truncation.
Operation
#define N_INT_SINGLE_RANGE 0xcf000000 & 0x7fffffff /* -1.000000 * 2^31 */
#define P_INT_SINGLE_RANGE 0x4effffff /* 1.fffffe * 2^30 */
#define N_INT_DOUBLE_RANGE 0xc1e0000000200000 & 0x7fffffffffffffff
#define P_INT_DOUBLE_RANGE 0x41e0000000000000
void FTRC(int m, int *FPUL)
{
pc += 2;
clear_cause();
if(FPSCR.PR==0){
case(ftrc_single_ type_of(m)){
NORM:
*FPUL = FR[m];
break;
PINF:
ftrc_invalid(0); break;
NINF:
ftrc_invalid(1); break;
}
}
else{
/* case FPSCR.PR=1 */
Rev. 3.00 Jul 08, 2005 page 318 of 484
REJ09B0051-0300