SH-2A Datasheet, PDF (319/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
11. This instruction transfers contents of memory at address indicated by (R0 + Rm) to FRn.
12. This instruction transfers contents of memory at address indicated by (R0 + Rm) to DRn.
13. This instruction transfers FRm contents to memory at address indicated by (R0 + Rn).
14. This instruction transfers DRm contents to memory at address indicated by (R0 + Rn).
Operation
void FMOV(int m,n)
/* FMOV FRm,FRn */
{
FR[n] = FR[m];
pc += 2;
}
void FMOV_DR(int m,n)
/* FMOV DRm,DRn */
{
DR[n>>1] = DR[m>>1];
pc += 2;
}
void FMOV_STORE(int m,n)
/* FMOV.S FRm,@Rn */
{
store_int(FR[m],R[n]);
pc += 2;
}
void FMOV_STORE_DR(int m,n) /* FMOV.D DRm,@Rn */
{
store_quad(DR[m>>1],R[n]);
pc += 2;
}
void FMOV_LOAD(int m,n)
/* FMOV.S @Rm,FRn */
{
load_int(R[m],FR[n]);
pc += 2;
}
void FMOV_LOAD_DR(int m,n) /* FMOV.D @Rm,DRn */
{
load_quad(R[m],DR[n>>1]);
pc += 2;
Rev. 3.00 Jul 08, 2005 page 305 of 484
REJ09B0051-0300