SH-2A Datasheet, PDF (46/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 3 Exception Handling
3.10 Usage Notes
3.10.1 Stack Pointer (SP) Value
Ensure that the stack pointer (SP) value is a multiple of 4. If it is not, an address error will be
caused when the stack is accessed in exception handling.
3.10.2 Vector Base Register (VBR) Value
Ensure that the vector base register (VBR) value is a multiple of 4. If it is not, an address error
will be caused when the vector is accessed in exception handling.
3.10.3 Address Errors Occurring in Address Error Exception Handling Stacking
If the stack pointer (SP) value is not a multiple of 4, an address error will occur in exception
handling (interrupt, etc.) stacking, and after the exception handling is completed, address error
exception handling will be started. An address error will also occur in stacking in the address
error exception handling, but this address error will not be accepted in order to prevent endless
stacking due to address errors. This enables program control to be switched to the address error
exception service routine, and error handling to be carried out.
When an address error occurs in exception handling stacking, the stacking bus cycle (write) is
executed. In SR and PC stacking, SP is decremented by 4 in each case, and therefore the SP value
is not a multiple of 4 after stacking is completed. Also, the address value output in stacking is the
SP value, and the actual address at which the error occurred is output. In this case, the stacked
write data is undefined.
Rev. 3.00 Jul 08, 2005 page 32 of 484
REJ09B0051-0300