SH-2A Datasheet, PDF (469/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(8) Double-Precision Floating-Point Register to Register Data Transfer Instructions
Instruction Types
FMOV DRm,DRn
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX EX
: CPU pipeline
IF DF EX EX NA SF
: FPU pipeline
IF ⋅ ⋅ ⋅ ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF ⋅ ⋅ ⋅ DF E1 E2 SF
: FPU pipeline
IF ⋅ ⋅ ⋅ ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF ⋅ ⋅ ⋅ DF E1 E2 SF : FPU pipeline
Operation
The CPU pipeline ends after four stages – IF, ID, EX, EX – and the FPU pipeline after six stages –
IF, DF, EX, EX, NA, SF. Contention does not occur even if one of these instructions is
immediately followed by an instruction that reads the destination of that instruction.
Instruction Issuance
This instruction uses the FPU load/store pipeline.
Parallel Execution Capability
No particular comments
Rev. 3.00 Jul 08, 2005 page 455 of 484
REJ09B0051-0300