SH-2A Datasheet, PDF (128/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.3.14 DIVU
DIVide as Unsigned
Unsigned Division
Arithmetic Instruction
SH-2A/SH2A-FPU (New)
Format
DIVU R0, Rn
Abstract
Unsigned, Rn ÷ R0 → Rn
Code
0100nnnn10000100
Cycle
34
T Bit
―
Description
Executes division of the 32-bit contents of a general register Rn (dividend) by the contents of R0
(divisor). This instruction executes unsigned division and finds the quotient only. A remainder
operation is not provided. To obtain the remainder, find the product of the divisor and the
obtained quotient, and subtract this value from the dividend.
Notes
A division by zero exception will occur if division by zero is performed.
If an interrupt is generated while this instruction is being executed, execution will be halted. The
return address will be the start address of this instruction, and this instruction will be re-executed.
Operation
DIVU (long n) /* DIVU R0, Rn */
{
(unsigned long) R[n]= (unsigned long)R[n] /
(unsigned long )R[0];
PC+=2;
}
Examples:
DIVU R0,R1
; R1(32bits) / R0(32bits) = R1(32bits); unsigned
Rev. 3.00 Jul 08, 2005 page 114 of 484
REJ09B0051-0300