SH-2A Datasheet, PDF (298/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.5.4
FCNVDS
Double-Precision
to Single-Precision
Conversion
Floating-point CoNVert
Double to Single precision
Floating-Point Instruction
PR Format
Abstract
0—
—
1 FCNVDS DRm,FPUL (float)DRm → FPUL
Code
Cycle
—
—
1111mmm010111101 2
T Bit
—
—
Description
When FPSCR.PR = 1, this instruction converts the double-precision floating-point number in
DRm to a single-precision floating-point number, and stores the result in FPUL.
When FPSCR.enable.O/U/I is set, an FPU exception trap is generated regardless of whether or not
an exception has occurred. When an exception occurs, correct exception information is reflected in
FPSCR.cause and FPSCR.flag, and FPUL is not updated. Appropriate processing should therefore
be performed by software.
If FPSCR.PR = 0, the instruction is handled as an illegal instruction.
Operation
void FCNVDS(int m, float *FPUL){
case((FPSCR.PR){
0: undefined_operation(); /* reserved */
1: fcnvds(m, *FPUL); break; /* FCNVDS */
}
}
void fcnvds(int m, float *FPUL)
{
pc += 2;
clear_cause();
case(data_type_of(m, *FPUL)){
NORM :
PZERO :
NZERO : normal_ fcnvds(m, *FPUL); break;
Rev. 3.00 Jul 08, 2005 page 284 of 484
REJ09B0051-0300