SH-2A Datasheet, PDF(188/501 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

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SH-2A Datasheet, PDF (188/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

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Section 6 Instruction Descriptions

Example:

MOV.L

BRSF

MOV

BSRF_PC:

#(TARGET-BSRF_PC),R0

R0

R3,R4

ADD R0,R1

.....

.....

TARGET:

MOV R2,R3

RTS

MOV #1,R0

; Sets displacement.

; Branches to TARGET

; Executes the MOV instruction before branching

; â The PC location is used to calculate the branch

destination with BSRF.

; âï Procedure entrance

;

; Returns to the above ADD instruction

; Executes MOV before branching

Note:

When a delayed branch instruction is used, the branching operation takes place after the

slot instruction is executed, but the execution of instructions (register update, etc.) takes

place in the sequence delayed branch instruction â delayed slot instruction. For example,

even if a delayed slot instruction is used to change the register where the branch

destination address is stored, the register content previous to the change will be used as the

branch destination address.

Rev. 3.00 Jul 08, 2005 page 174 of 484

REJ09B0051-0300

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