SH-2A Datasheet, PDF (73/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 5 Instruction Set
Instruction
CLIPS.W Rn
CLIPU.B Rn
CLIPU.W Rn
DIV1
Rm, Rn
DIV0S Rm, Rn
DIV0U
DIVS
R0, Rn
DIVU R0, Rn
DMULS.L Rm, Rn
DMULU.L Rm, Rn
DT
Rn
EXTS.B Rm, Rn
EXTS.W Rm, Rn
EXTU.B Rm, Rn
EXTU.W Rm, Rn
MAC.L @Rm+,
@Rn+
MAC.W @Rm+,
@Rn+
MUL.L Rm, Rn
Compatibility
Code
Operation
Cycles
T Bit
New
SH2E
SH4
SH-2A/
SH2A-
FPU
0100nnnn10010101 When Rn > (H'00007FFF),
1
―
Yes
(H'00007FFF) → Rn, 1 → CS
When Rn < (H'FFFF8000),
(H'FFFF8000) → Rn, 1 → CS
0100nnnn10000001 When Rn > (H'000000FF),
1
―
Yes
(H'000000FF) → Rn, 1 → CS
0100nnnn10000101 When Rn > (H'0000FFFF),
1
―
Yes
(H'0000FFFF) → Rn, 1 → CS
0011nnnnmmmm0100 1-step division (Rn ÷ Rm)
1 Calculati- Yes Yes
on result
0010nnnnmmmm0111 MSB of Rn → Q, MSB of Rm → M,
M^Q→T
1 Calculati- Yes Yes
on result
0000000000011001 0→M/Q/T
1
0
Yes Yes
0100nnnn10010100 Signed, Rn ÷ R0 → Rn
36
―
Yes
32 ÷ 32 → 32 bits
0100nnnn10000100 Unsigned, Rn ÷ R0 → Rn
34
―
Yes
32 ÷ 32 → 32 bits
0011nnnnmmmm1101 Signed, Rn × Rm → MACH, MACL
2
―
Yes Yes
32 × 32 → 64 bits
0011nnnnmmmm0101 Unsigned, Rn × Rm → MACH,
MACL
2
―
Yes Yes
32 × 32 → 64 bits
0100nnnn00010000 Rn - 1 → Rn; when Rn = 0, 1 → T
When Rn ≠ 0, 0 → T
1 Com-
Yes Yes
parison
result
0110nnnnmmmm1110 Rm sign-extended from byte → Rn
1
―
Yes Yes
0110nnnnmmmm1111 Rm sign-extended from word → Rn 1
―
Yes Yes
0110nnnnmmmm1100 Rm zero-extended from byte → Rn
1
―
Yes Yes
0110nnnnmmmm1101 Rm zero-extended from word → Rn 1
―
Yes Yes
0000nnnnmmmm1111 Signed, (Rn) × (Rm) + MAC
→ MAC
4
―
Yes Yes
32 × 32 + 64 → 64 bits
0100nnnnmmmm1111 Signed, (Rn) × (Rm) + MAC
→ MAC
3
―
Yes Yes
16 × 16 + 64 → 64 bits
0000nnnnmmmm0111 Rn × Rm → MACL
2
―
Yes Yes
32 × 32 → 32 bits
Rev. 3.00 Jul 08, 2005 page 59 of 484
REJ09B0051-0300