SH-2A Datasheet, PDF (280/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.4.63
SWAP
Upper-/Lower-Half
Swap
SWAP register halves
Data Transfer Instruction
Format
SWAP.B Rm,Rn
SWAP.W Rm,Rn
Abstract
Rm → Swap upper and lower
halves of lower 2 bytes → Rn
Rm → Swap upper and lower
word → Rn
Code
Cycle T Bit
0110nnnnmmmm1000 1
—
0110nnnnmmmm1001 1
—
Description
Swaps the upper and lower bytes of the general register Rm data, and stores the result in Rn. If a
byte is specified, bits 0 to 7 of Rm are swapped for bits 8 to 15. The upper 16 bits of Rm are
transferred to the upper 16 bits of Rn. If a word is specified, bits 0 to 15 of Rm are swapped for
bits 16 to 31.
Operation
SWAPB(long m,long n) /* SWAP.B Rm,Rn */
{
unsigned long temp0,temp1;
temp0=R[m]&0xffff0000;
temp1=(R[m]&0x000000ff)<<8;
R[n]=(R[m]>>8)&0x000000ff;
R[n]=R[n]|temp1|temp0;
PC+=2;
}
SWAPW(long m,long n) /* SWAP.W Rm,Rn */
{
unsigned long temp;
temp=(R[m]>>16)&0x0000FFFF;
R[n]=R[m]<<16;
R[n]|=temp;
PC+=2;
}
Rev. 3.00 Jul 08, 2005 page 266 of 484
REJ09B0051-0300