SH-2A Datasheet, PDF (312/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.5.11
FMAC
Floating-point Multiply
and ACcumulate
Floating-Point Multiply
and Accumulate
Floating-Point Instruction
PR Format
Abstract
0 FMAC FR0,FRm,FRn FR0*FRm+FRn → FRn
1—
—
Code
Cycle
1111nnnnmmmm1110 1
—
—
T Bit
—
—
Description
When FPSCR.PR = 0, this instruction arithmetically multiplies the two single-precision floating-
point numbers in FR0 and FRm, arithmetically adds the contents of FRn, and stores the result in
FRn.
When FPSCR.enable.O/U/I is set, an FPU exception trap is generated regardless of whether or not
an exception has occurred. When an exception occurs, correct exception information is reflected in
FPSCR.cause and FPSCR.flag, and FRn is not updated. Appropriate processing should therefore
be performed by software.
If FPSCR.PR = 1, the instruction is handled as an illegal instruction.
Operation
void FMAC(int m,n)
{
pc += 2;
clear_cause();
if(FPSCR_PR == 1) undefined_operation();
else if((data_type_of(0) == sNaN) ||
(data_type_of(m) == sNaN) ||
(data_type_of(n) == sNaN)) invalid(n);
else if((data_type_of(0) == qNaN) ||
(data_type_of(m) == qNaN)) qnan(n);
else if((data_type_of(0) == DENORM) ||
(data_type_of(m) == DENORM)) set_E();
else switch (data_type_of(0){
case NORM: switch (data_type_of(m)){
Rev. 3.00 Jul 08, 2005 page 298 of 484
REJ09B0051-0300