SH-2A Datasheet, PDF (81/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 5 Instruction Set
Instruction
Code
Operation
FMOV.S @(disp12,Rm),FRn 0011nnnnmmmm0001 (disp×4+Rm) → FRn
0111dddddddddddd
FMOV.D @(disp12,Rm),DRn 0011nnn0mmmm0001 (disp×8+Rm) → DRn
0111dddddddddddd
FMOV.S FRm, @( R0,Rn ) 1111nnnnmmmm0111 FRm → (R0+Rn)
FMOV.D DRm, @( R0,Rn ) 1111nnnnmmm00111 DRm → (R0+Rn)
FMOV.S FRm, @-Rn
1111nnnnmmmm1011 Rn- = 4, FRm → (Rn)
FMOV.D DRm, @-Rn
1111nnnnmmm01011 Rn- = 8, DRm → (Rn)
FMOV.S FRm, @Rn
1111nnnnmmmm1010 FRm → (Rn)
FMOV.D DRm, @Rn
1111nnnnmmm01010 DRm → (Rn)
FMOV.S FRm, @(disp12,Rn) 0011nnnnmmmm00010 FRm → (disp×4+Rn)
011dddddddddddd
FMOV.D DRm, @(disp12,Rn) 0011nnnnmmm000010 DRm → (disp×8+Rn)
011dddddddddddd
FMUL FRm, FRn
1111nnnnmmmm0010 FRn × FRm → FRn
FMUL DRm, DRn
1111nnn0mmm00010 DRn × DRm → DRn
FNEG FRn
1111nnnn01001101 -FRn → FRn
FNEG DRn
1111nnn001001101 -DRn → DRn
FSCHG
1111001111111101 FPSCR.SZ = ~ FPSCR.SZ
FSQRT FRn
1111nnnn01101101 √FRn → FRn
FSQRT DRn
1111nnn001101101 √DRn → DRn
FSTS FPUL,FRn
1111nnnn00001101 FPUL → FRn
FSUB FRm, FRn
1111nnnnmmmm0001 FRn - FRm → FRn
FSUB DRm, DRn
1111nnn0mmm00001 DRn - DRm → DRn
FTRC FRm, FPUL
1111mmmm00111101 (long) FRm → FPUL
FTRC DRm, FPUL
1111mmm000111101 (long) DRm → FPUL
Cycles
1
2
1
2
1
2
1
2
1
2
1
6
1
1
1
9
22
1
1
6
1
2
T Bit
―
Compatibility
SH2E
SH4
New
SH-2A/
SH2A-
FPU
Yes
―
Yes
― Yes Yes
―
Yes
― Yes Yes
―
Yes
― Yes Yes
―
Yes
―
Yes
―
Yes
― Yes Yes
―
Yes
― Yes Yes
―
Yes
―
Yes
―
Yes
―
Yes
― Yes Yes
― Yes Yes
―
Yes
― Yes Yes
―
Yes
Rev. 3.00 Jul 08, 2005 page 67 of 484
REJ09B0051-0300