SH-2A Datasheet, PDF (343/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 Register Banks
External interrupt
2+m1+m2+m3
2
m1 m2 m3
m1: Vector address read
m2: SR save (stack)
m3: PC save (stack)
Instruction (instruction replacing
interrupt exception
processing)
Overrun fetch
F D E EMMM
(1)VTO,PR,GBR,MACL
(2)R12,R13,R14,MACH
(3)R8,R9,R10,R11
Save to bank
(4)R4,R5,R6,R7
(5)R0,R1,R2,R3
F
First instruction in interrupt service routine
FDE
Figure 7.3 Bank Save Timing
7.3.2 Retrieve from Bank
The retrieve from bank instruction, RESBANK, is used to retrieve data stored in a bank. After
retrieving the data from the bank with the RESBANK instruction at the end of the interrupt service
routine, use the RTE instruction to return from exception processing.
7.3.3 Save and Retrieve Operations after Saving to All Banks
If, after data has been saved to all of the register banks, an interrupt for which register bank use is
allowed is received by the CPU, data is saved automatically to the stack instead of a register bank.
This is possible by masking the register bank overflow exception using the interrupt controller. If
a register bank overflow exception were generated it would not be possible to save to the stack.
For details, refer to the Interrupt Controller section of the hardware manual for the product in
question. The automatic save to and retrieve from stack operations are described below.
(1) Save to Stack
(a) When interrupt exception processing occurs, the status register (SR) and program counter
(PC) are saved on the stack.
(b) The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are saved
to the stack. The order in which the contents of these registers are saved is MACL, MACH,
GBR, PR, R14, R13, … R1, R0.
(c) The register bank overflow bit in SR is set to 1.
(d) The bank number (BN) bits in the bank number register (IBNR) remain set to the
maximum value, N.
Rev. 3.00 Jul 08, 2005 page 329 of 484
REJ09B0051-0300