SH-2A Datasheet, PDF (45/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 3 Exception Handling
3.9 Stack Status after Exception Handling
Table 3.10 shows the stack status after completion of exception handling.
Table 3.10 Stack Status after Exception Handling
Type
Address
error
SP
Stack Status
Type
Interrupt
Address of instruction (32 bits)
SP
following executed
instruction
SR
(32 bits)
Stack Status
Address of instruction
following executed
instruction
SR
(32 bits)
(32 bits)
RAM error
SP
Address of instruction
following executed
instruction
SR
(32 bits)
(32 bits)
Register
bank error
(overflow) ^SP
Address of instruction
following executed
instruction
SR
(32 bits)
(32 bits)
Register
bank error
(underflow)
SP
Start address of
relevant RESBANK
instruction
SR
(32 bits)
(32 bits)
Integer
division
instruction
SP
(division
by zero,
overflow)
Start address of
relevant integer
division instruction
SR
(32 bits)
(32 bits)
Trap
instruction
SP
Address of instruction
following TRAPA
instruction
SR
(32 bits)
(32 bits)
Slot illegal
instruction
SP
Jump destination
address of delayed
branch instruction
SR
(32 bits)
(32 bits)
General
illegal
instruction ^SP
Start address of
general illegal
instruction
SR
(32 bits)
FPU
exception
SP
(32 bits)
Address of instruction
following executed
instruction
SR
(32 bits)
(32 bits)
Rev. 3.00 Jul 08, 2005 page 31 of 484
REJ09B0051-0300