SH-2A Datasheet, PDF (474/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
Instruction Issuance
These instructions use the FPU load/store pipeline and memory access pipeline.
Parallel Execution Capability
This is a 32-bit instruction, and cannot be used in parallel execution. (See section 8.3.5, Details of
Contention Due to 32-Bit Instruction.)
Rev. 3.00 Jul 08, 2005 page 460 of 484
REJ09B0051-0300